The present invention relates to a method and apparatus for evaluating a logic circuit of an integrated circuit device such as a semiconductor substrate or printed-circuit board in a short period of time, to a method and apparatus for estimating the product specifications of the integrated circuit device, and to a CAD method and apparatus for assisting the layout design of the integrated circuit device. It particularly relates to a method and apparatus for properly classifying and evaluating a logic circuit, to a method and apparatus for creating a product specification database for an existing integrated circuit device, to a method and apparatus for estimating the product specifications of an integrated circuit to be manufactured, and to a method and apparatus for automatically organizing a logic circuit in a hierarchical structure so that the layout design of the integrated circuit device can be carried out at high speed.
In recent years, it has become possible to realize a large-scale integrated circuit on a single LSI chip or on a small number of printed-circuit boards due to the improvements in fabrication techniques, such as the multi-layer wiring technique and microprocessing, for producing integrated circuit device or printed-circuit boards.
As a larger-scale integrated circuit system has been realized on a LSI chip or on printed-circuit boards, design automation (DA) techniques for automating the layout design process of a logic circuit have been developed.
However, as the number of the logic elements to be designed becomes larger, the time required by an electronic calculator for processing has become extremely long with a conventional method and apparatus. Moreover, the deterioration in quality of the result of the automatic processing has been causing problems.
In general, the operational specification is identified by using an estimated wire length (wire length calculated in terms of the circuit scale based on statistics). However, in the case where the estimated wire length differs greatly from the real wire length in the final product, it is required to design or lay out the logic circuit again, which results in a waste of labor.
To prevent such a disadvantage, there is a case where a logic circuit is designed by using a redundant estimated wire length in consideration of the dispersion in value of the estimated wire length. However, this necessitates the provision of a signal output device for outputting a signal to the redundant lines, resulting in the increase in layout area and fabrication cost.
The layout area of an LSI is generally calculated on the basis of a value obtained by multiplying the total element area by a constant. However, the obtained layout area and hence fabrication cost of the LSI present values with errors which are often twice as large as the real values or more.
In addition, if a long-term designing operation is repeatedly performed with the above-mentioned DA techniques, the period and cost required for the development of the LSI are disadvantageously increased.
In view of these circumstances, there has been a demand for the establishment of a method which uses existing design data, logic circuits, and their layouts as product specifications so as to reduce the designing period, to compensate for the ambiguous estimation, to estimate product specifications with high precision prior to the layout design, and to perform the overall DA process at high speed. Specifically, there has been a demand for the following techniques:
(1) a technique of reusing existing logic circuits (design assets) efficiently; PA1 (2) a technique of estimating with high precision the product specifications of an integrated circuit device to be manufactured; and PA1 (3) a technique of performing the DA process at high speed by organizing a logic circuit in a hierarchical structure.
For the efficient utilization of existing logic circuits, it is necessary to classify the existing logic circuits. It is also necessary to create a product specification database based on the method of classification.
With conventional techniques, logic circuits are mostly classified in terms of their functions. As a method to store data on a logic circuit, accordingly, a product specification database is created in terms of individual functions.
However, even with logic circuit blocks having similar functions, their structures differ greatly depending on the processing speed, layout area, and power consumption. Therefore, it is necessary to establish a method of calculating a value for classification in view of the present circumstances and a method of creating a product specification database on the basis of the value for classification.
The effect of the hierarchical organization of logic circuit elements on the processing speed can be estimated as follows. Suppose that the processing time T with a specific technique for dividing a logic circuit is the square of the number N of their logic elements, i.e., T is proportional to N.sup.2. If the logic elements are hierarchically organized so that N becomes N/2, the processing time required to organize the logic elements in a hierarchical structure is proportional to (N/2).sup.2, as expressed in the following equation (1). Consequently, the processing time is reduced to a forth of the original time by halving the elements. EQU T'=T/4 (1)
However, the result of the process of hierarchical organization normally deteriorates in quality, as indicated in a book (Sivanarayana Mallela and Lov K. Grover, "Clustering based Simulated Annealing for Standard Cell Placement," 25-th ACM/IEEE Design Automation Conference, pp. 312-317, 1988). In the book mentioned above, the deterioration in quality of the processing result in generating clusters (a type of hierarchy) is prevented by limiting the magnitude of a cluster with a given constant.
However, the optimum magnitude of a cluster in hierarchical organization varies depending on the type and property of a logic circuit. Accordingly, it becomes necessary to establish a method of hierarchical organization which can determine the magnitude of a cluster by considering the characteristics of a logic circuit. For this purpose also, it is required to calculate the value for classification that reflects the characteristics of a logic circuit.
From the foregoing description, it will be understood that the most important technique in establishing the above-mentioned method is of calculating the value for classifying a logic circuit.
Some conventional techniques for classifying and evaluating a logic circuit utilize as the value for classification a relatively large logic function, called a functional block, of the logic circuit, while others utilize a ratio of the number of logic elements to the number of lines (hereinafter referred to as net number) as the value for classification.
However, since there are a variety of logic circuits which have the same number of elements and the same number of lines, it is impossible to establish a specific relationship between the layout and the ratio of the number of elements to the number of lines. In principle, it is difficult to obtain, from the number of elements and lines thereof, the classification value for use in estimating the layout design of a logic circuit. This is because the layout design is physically or spatially restricted in that it is definitely two dimensional, while the design of a logic circuit has no physical or spatial limitations.
Hence, it will be understood that, if the physical or spatial range of a logic circuit is utilized as the value for classification, it can serve as an indicator in estimating the relationship between the design of the logic circuit and the layout design thereof.
Among the methods utilizing the physical or spatial range of a logic circuit as the value for classification, there is a method which utilizes the numerical relationship between a logic circuit and its layout as the value for classifying the logic circuit by its logic function, for the layout area varies greatly depending on the function of the logic circuit. There is also another method which utilizes the relationship between the number of elements and the net number as the value for classification, for the result of the layout reflects such factors as element area, element number, and net number.
In the case where logic function is utilized as the value for classifying a logic circuit, it is classified in terms of its logic function such as an adder, multiplier, and data path. If a synthesized system is introduced based on the logic function in designing the logic circuit, various logic circuits having the same logic function may result, depending on control factors such as a high-speed operation and minimized area, in a process of automatically connecting specific logic elements based on the design concept of the logic circuit to be realized. Thus, the utilization of a logic function as the reference for classifying a logic circuit is disadvantageous in that the individual characteristics of logic circuits are not reflected in their calculated values for classification.
Consequently, it becomes impossible to estimate product specifications of a logic circuit. To satisfy the functional specification and cost specification of a product, it becomes necessary to repeatedly perform the designing operation with the DA techniques over a long period of time, resulting in an increase in period and cost for the development of an LSI. It is known that the number of elements in a logic circuit differs depending on the system adopted. For example, the number of elements in a logic circuit serving as a 4-bit adder may double depending on whether it adopts the carry look ahead system or ripple carry system. This exemplifies the difficulty in precisely estimating the product specifications of the logic circuit when the value for classification is determined by its logic function.
Also in the method utilizing the ratio of net number to number of elements as the value for classifying a logic circuit, there is a case where the properties of logic circuits, such as the ranges of their lines, are different even with circuits having the same ratio of net number to number of elements. Logic circuits shown in FIGS. 10(a), 10(b), and 10(c) exemplify the case. Each of the logic circuits of FIG. 10(a) and FIG. 10(b) presents Net Number/Element Number=2, which shows that the logic circuits have the same classification value in common.
However, the net list of the logic circuit of the FIG. 10(b) indicates a one-dimensional connection, so that the logic circuit of FIG. 10(b) is less similar than to the logic circuit of FIG. 10(a) than it is to the logic circuit of FIG. 10(c) which has Net Number/Element Number=1 as the value for classification. This proves that the characteristics of a logic circuit are not precisely reflected in the classification value calculated from the ratio of net number to number of elements.
As described above, the classification value calculated from the ratio of net number to number of elements, which has conventionally been used, is disadvantageous as a reliable indicator in classification.